1. Field of the Invention
The present invention relates generally to analog-to-digital converters and more particularly to subranging analog-to-digital converters.
2. Description of the Related Art
As shown in various references (e.g., Kester, Walt, et al., High Speed Design Techniques, Analog Devices, Inc., Norwood, Mass. 1996), a subranging analog-to-digital converter (ADC) generally has N successive converter stages so that it has at least one combination of a prior converter stage and a corresponding subsequent converter stage. Except for a terminal stage, each converter stage quantizes an analog input signal into a respective number of digital bits, subtracts from the input signal an analog signal corresponding to the digital bits and passes the resulting residue signal to its corresponding subsequent converter stage for further quantization. The terminal converter stage receives the last residue signal and generates a corresponding set of least significant bits.
As illustrated in FIG. 1, an exemplary subranging ADC 20 includes a prior converter stage 22 and a subsequent converter stage 24. In the prior converter stage, a prior sampler 28 forms a sampled input signal 30 from an analog input signal 32. The sampled signal is quantized by a prior ADC 34 in the prior converter stage to form a set of prior digital bits 35 that are stored in a buffer register 36.
A prior digital-to-analog converter (DAC) 40 responds to the prior digital bits 35 by forming a corresponding analog signal 42 and this signal and the sampled input signal 30 are differenced in a subtractor 44 to form a residue signal 46 which is amplified by a residue amplifier 48 to provide a signal range to the subsequent converter stage that can be effectively processed. To enhance formation of the residue signal, the sampled input signal 30 is typically delayed by a delay 50 which is often formed with another sampler.
In the subsequent converter stage 24, the residue signal 46 is sampled in a subsequent sampler 52 and quantized by a subsequent ADC 54 to form a set of subsequent digital bits 55 that are less significant than the prior digital bits 35. Both sets of digital bits are communicated to output registers 58 to form a digital output 60 that corresponds to the analog input signal 32. The subranging ADC 20 may also include an error correction logic system 56. In this case, the prior converter stage 24 generally quantizes at least one more digital bit than required and this process is combined with the error correction logic 56 to correct many of the conversion errors of typical uncorrected ADCs.
If the subsequent converter stage 24 is the terminal converter stage, the digital bits 55 are the least significant bits of the conversion process. Otherwise, the subsequent converter stage contains further structure that is similar to that of the prior converter stage as indicated by broken lines 62. With this additional structure it can generate and pass a residue signal to its respective subsequent converter stage. The prior and subsequent ADCs 34 and 54 are typically formed with a serial arrangement of single-bit ADCs (e.g., preliminary stages of folding amplifiers and a final comparator stage).
To prevent converter errors (e.g., non-linearities and missing codes), the range of each residue signal must match the signal input range of its subsequent converter stage. Because subranging ADCs generally process differential signals, this range match can only be realized if the magnitude of the residue signal is proper and if its common-mode level approximates a predetermined level. Differences from the predetermined level (i.e., offset errors) must be controlled and reduced to an acceptable level.
Operational processes in the subtractor 44 and the residue amplifier 48 generally include the noise-generation process of passing currents through resistors. This noise generation is often reduced by eliminating the subtractor 44 of FIG. 1 and performing its processes with currents that pass through gain-setting resistors within the residue amplifier. In order to match the range magnitude of the subsequent converter stage, the gain of the residue amplifier is generally substantial so that the gain-setting resistors have large resistances (e.g., &gt;1000 ohms).
In one conventional control system, offset errors are reduced by inserting a fixed, predetermined offset current across the gain-setting resistors. Because of the large resistance of these resistors, small errors in the fixed offset current are magnified and an uncorrected offset error results. In addition, application of a fixed offset current in one converter stage has no effect on uncorrected offset errors in a prior converter stage.
In another conventional control system, the fixed current source is replace with a variable one that is responsive to a feedback control loop that is formed around the residue amplifier 48. In this loop, the residue signal offset is sensed at the output of the residue amplifier 48, compared with a reference signal in an integrator to generate an error signal, and the error signal applied to the variable offset current source.
As mentioned above, the residue amplifier 48 typically has a substantial gain. It therefore magnifies spurious signals that are generated by cell switching in the prior DAC 40 and the feedback loop causes the common-mode level to change on a clock-to-clock basis. The resulting degradation in converter performance becomes particularly troublesome at high speed clock rates (e.g., on the order of 80 million samples per second (MSPS)).